1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of switching between different clocks in data processing systems
2. Description of the Prior Art
When switching between clocks in a data processing system, if the switching is not controlled then glitches, or skinny/runt pulses can occur. This can cause problems with the processing system and is better avoided. FIG. 1 shows an example of a glitch pulse being produced when uncontrolled switching from a slower REF clock to a faster clock occurs.
One way of addressing this problem is with the use of registers which control the time at which the switching is allowed. In the embodiment shown in FIG. 2, the switch is relayed through clocked registers, such that when the refclock is low, at point shown by dotted line (1), the switch signal is passed to the next register, register 2 then when the fstclk goes high dotted line (2), it passes to the next register, register 3, and when fstclk falls low, dotted line (3), the switch is operable and the clock output switches from the ref clock to the fast clock. This system ensures that the refclock is low (and thus the output clock is low) when the clocks switch and also that the fast clock has just switched to its low value at this point. Thus, it ensures that we switch from a low clock level to a low clock level and that we switch at the start of the fast clock's low pulse thereby ensuring both clocks are low and thus no smaller pulses or glitches can be produced. This system only works if refclk does not switch during stage 2 and 3 (between dotted lines 2 and 3), i.e. while the fstclk is in the high state. In other words it will only work when switching from a slower to a faster clock and not vice versa.
It would be desirable to provide a glitch-free or at least reduced glitch way of switching between clocks in either direction, i.e. from both a slower to a faster clock and from a faster to a slower clock.